module count (
    clk,
    nrst,
    count
);
    input clk;
    input nrst;
    output [7:0] count;
    reg [7:0] count_q;

assign count = count_q;

always @(posedge clk) begin
    if (~rst) begin
        count_q <= 0;
    end else begin
        count_q <= count_q + 1;
    end
end

endmodule